1. Field of the Invention
The present invention relates to an instruction cache and a microprocessor (MPU) in which the instruction cache is provided, and a method of designing the same, and in particular, to a circuit and a method aiming to reduce electric power consumption of an MPU. The present invention is applied to, for example, a configurable processor or the like.
2. Description of the Related Art
In recent years, for example, an instruction cache which is a small capacity but high speed storage device is provided in a general 32-bit MPU in order to reduce the memory access latency for a low speed main memory. In such an MPU, there are many cases based on a procedure in which, at the time of executing an instruction in the main memory at high speed, the instruction read from the main memory in advance is temporarily stored in an instruction cache (on-chip instruction cache), and at the time of reading the same instruction again, the instruction temporarily stored in the instruction cache, and not in the main memory, is used.
FIG. 2 shows a state in which instruction codes on an external main memory are stored in the instruction cache provided in the MPU.
With regard to the data stored in the instruction cache, an instruction code (cache data) and the position of the cache data (Cache Data) on the main memory and a flag showing the validity/invalidity are made to be one set, with an address (Addr) generated from the position of the instruction code on the main memory serving as an index (Index). Here, due to restrictions on the capacity of the instruction cache and in order to efficiently utilize the capacity, one tag and a fixed amount of continuous regions on the main memory correspond to one index.
FIG. 8 shows an example of a conventional instruction cache provided in an MPU.
The instruction cache has an instruction cache controller 81, an instruction cache data memory 82, an instruction cache tag memory 83, and a hit/miss determining circuit (comparator) 84.
In the instruction cache, some of bit signals of access addresses supplied via the instruction cache controller 81 from a fetching counter (not shown) provided in the MPU are inputted to the instruction cache data memory 82, the instruction cache tag memory 83, and the hit/miss determining circuit 84, respectively.
As shown in FIG. 2, the aforementioned cache data memory 82 is configured to have a plurality of cache lines for storing a plurality of words (in this example, 1 word is 32 bits and shows the unit of one instruction) having successive access addresses. Further, readout data are outputted in accordance with access addresses inputted from the MPU.
The instruction cache tag memory 83 stores data required for specifying words stored in the respective cache lines, for each cache line of the instruction cache data memory 82. Further, when a memory enable (MEMORY Enable) signal inputted from the instruction cache controller 81 by a data readout request from the MPU becomes active, the data is read in accordance with the inputted access address.
The aforementioned hit/miss determining circuit 84 compares an address input read from the instruction cache tag memory 83 and the access address inputted from the MPU, and determines whether they match/do not match (determines whether or not the aforementioned word having the access address is stored in the instruction cache data memory 82) to generate the results of determination as a hit/miss determining signal. In parallel with the operation of the hit/miss determining circuit 84, cache data (an instruction) is read from the instruction cache data memory 82, and outputted to the instruction cache controller 81.
The instruction cache controller 81 decides whether or not the cache data read from the instruction cache data memory 82 is to be fetched into an instruction fetching register of the MPU, in accordance with the hit/miss determining signal from the hit/miss determining circuit 84.
As described above, the instruction cache outputs to the MPU the readout data of 32 bits as an instruction and the hit/miss determining signal of 1 bit expressing whether or not the instruction cache has hit.
In the case of a hit, the MPU fetches the data from the instruction cache data memory 82, and in the case of a miss, the MPU does not fetch the data from the instruction cache data memory 82.
In the case of a miss, an access address is outputted from the instruction cache to the main memory (not shown), and the 32-bit data as the instruction is read from the main memory and outputted to the instruction cache.
FIG. 9 shows an operation flow when the MPU obtains an instruction code from the conventional instruction cache shown in FIG. 8.
At the time of reading the instruction cache at the MPU, when read process of the instruction cache is started by a data readout request, an index number of the instruction cache is prepared from the address stored in the instruction cache which the MPU reads out. Then, corresponding data is obtained from the index number.
Next, it is determined whether or not the indexed cache data is valid. As a result, if it is determined that the indexed cache data is not valid (N), the routine proceeds to a process for reading out an instruction from the main memory, and the readout process of the instruction cache ends (END).
On the other hand, if the cache data is valid (Y), it is determined whether or not the cache data and the address to be read out from the instruction cache are the same. As a result, if they are determined to be the same (Y), the routine proceeds to a process for reading out the instruction from the instruction cache, and the readout process of the instruction cache ends (END). On the contrary, when it is determined that they are not the same (N), the routine proceeds to a process for reading out the instruction from the main memory, and the readout process of the instruction cache ends (END).
The process from Start to End shown in FIG. 9 is repeated for each time the MPU executes one instruction. The block portions enclosed by double lines in the operation flow (process of obtaining tag data from the index number, process of reading the instruction out from the cache memory, and process of reading the instruction out from the main memory) are operations in which a large quantity of electric power is consumed.
By the way, many of the execution instructions of the MPU are non-branch instructions. Here, a branch instruction is a generic expression for instructions which are such that the count value of the fetch counter in the processor 14 jumps, such as jump instructions, subroutine calling instructions, interruption instructions, or the like.
When the MPU executes a non-branch instruction, the instruction cache tag memory is repeatedly read out at the same index, since the instruction codes stored in the main memory are executed in order.
For example, in the example of the instruction codes shown in FIG. 2, at the time of continuously executing the instructions from Code 00 to Code 11, the index at the time of reading out the tag memory is BBBBCCCCDDDD. At this time, even when accessing is carried out at the same index, the same operation is repeated, and the repeated operations have been a cause of an increase in electric power consumption.
As described above, in a conventional MPU, when non-branch instructions which account for the majority of execution instructions are executed, regardless of the fact that the address of the tag memory which is read out prior to reading of the instruction cache is the same, because reading of the tag memory is carried out each time the instruction cache is read, there is the problem that electric power is consumed unnecessarily.
In order to suppress an increase in the electric power consumption of the instruction cache, it has been proposed that operation of the tag memory of the instruction cache be controlled by using a branch instruction detecting signal generated when a branch instruction is detected at the MPU, in “Instruction Cache Memory” of Jpn. Pat. Appln. KOKAI Publication No. 2000-200217.